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ADV7195
HSYNC
VSYNC
A
DV
PIXEL
DATA
Y
Cr
Cb
Y
Cr
Cb
Y
Cr
Cb
Y
Cr
Cb
B
A MIN = 16 CLK CYCLES (525P)
A MIN = 12 CLK CYCLES (625P)
A MIN = 44 CLK CYCLES (1080I)
A MIN = 70 CLK CYCLES (720P)
B MIN = 122 CLK CYCLES (525P)
B MIN = 132 CLK CYCLES (625P)
B MIN = 236 CLK CYCLES (1080I)
B MIN = 300 CLK CYCLES (720P)
Figure 4. Input Timing Diagram
SDA
SCL
t 3
t 6
t 1
t 5
t 3
t 2
t 7
t 4
t 8
Figure 5. MPU Port Timing Diagram
REV. A
–7 –
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